1. Field of the Invention
The present invention relates to a test apparatus and a control method. More particularly, the present invention relates to a test apparatus and a control method for sending an instruction for control from a control processor to a test unit in order to control the test unit that tests a device under test.
2. Related Art
A control processor provided in a test apparatus operates based on an installed control program and sends an instruction to a test unit. In this way, it is possible to control the test unit, for example, to appropriately start the test unit or to change a setting for the test unit under an operation.
However, a sequence of instructions to be processed is determined according to a specification in the test unit, and when an execution sequence of the instructions is contrary to the specification, it is concerned that the test unit and a device under test are damaged. For this reason, a programmer makes the control program so as to execute the instructions in a sequence based on this specification.
Moreover, a timing at which the instructions should be executed is determined according to the specification in the test unit. For example, a certain instruction is determined to be executed at a timing at which the test unit enters a predetermined state. A method for detecting such a state change includes polling by a control processor or interrupt-handling for a control processor from a test unit.
The polling by a control processor means a process by which the control processor regularly reads a value of a register in the test unit and detects a state change by means of the change of value. However, since the process reading a value from the register has a long time distance in comparison to an instruction execution by the control processor and an input-output waiting time occurs for the control processor, computing powers of the control processor may not be effectively used.
On the other hand, when trying to realize interrupt handling, each test unit needs a mechanism for realizing the interrupt handling, and thus it is concerned that a whole design of the test apparatus is complicated. Furthermore, when trying to quickly detect interrupt, presence or absence of the interrupt should be confirmed at high frequency, and thus it is concerned that an operating system for controlling interrupt increases a processing load of the control processor.
In this manner, when trying to quickly and appropriately detect the state change of the test unit, the control processor requires high computing powers. For this reason, although the test apparatus includes a plurality of test units, control processors are needed every test unit and thus a number of control processors are mounted in the test apparatus. The increase of the number of the control processors results in jumboization of the test apparatus and a cooling apparatus and the increase of cost, and then may cause the increase of an incidence rate of failure of the test apparatus.
In addition, as a reference technique related to a semiconductor test apparatus, the Japanese Patent Application Publication No. 1999-64450 can be referred to.